R&D teams are 'separable' says biz, which is open to offers for parts or the whole European RISC-V biz Codasip has put itself ...

Ubuntu 25.10 bumps its baseline RISC-V ISA profile family from RVA20 to RVA23. An RVA (RISC-V Vector Architecture) profile is ...

Chipmaker Loongson says server CPUs on par with 2021’s Ice Lake, as local press tout kit to manage 1,024-qubit systems ...

According to the company, its self-developed Haawking-HX2000 DSP chip series, the world's first based on RISC-V architecture, ...

Arm's royalty rates for its newest architecture, v9, are around 5%, double those of predecessor v8, according to management. As v9 represents a larger portion of revenue, Arm's blended royalty rate ...

Innatera's PULSAR is the first mass-market neuromorphic microcontroller, designed to bring brain-inspired AI to the sensor ...

The Yocto Project, an open source collaboration project that helps developers create custom Linux-based systems regardless of ...

Typically, since their inception, they have been x86 architecture-based, whereas nearly the entire world's smartphones are ...

That bottom‑up push is now backed from the top: on 29 March 2025, China’s Ministry of Industry & Information Technology (MIIT) and the Cyberspace Administration of China published draft guidelines ...

Cyient Semiconductors and MIPS announce collaboration to develop custom RISC-V-based intelligent power solutions.

Abstract. CHIPS Alliance has developed an open-source riscv-dv random instruction generator for RISC-V processor verification. This article focuses on the class riscv_asm_program_gen.sv and its ...