The A12B50M is an ultra low-power, pipeline analog to digital converter (ADC) intellectual property (IP) design block. It has 12-bit resolution and a sampling rate of up to 50 megasamples per second ...

Using the enable scorecard, it is easy to analyze different blocks for clock activity and learn how much more clock gating is possible to reduce the activity. For example, the design unit “mc_cont” in ...

Book Abstract: "Do you want to design a wireless transmitter or receiver for hand-held telephones? Have you wondered why the printed circuit wires on high-frequency circuits don't always run in a ...